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| Jul '09 CONFIDENTIAL CS61535A T1/E1 Line Interface Features General Description The CS61535A combines the complete analog transmit and receive line interface for T1 or E1 applications in a low power, 28-pin device operating from a +5V supply. The device features a transmitter jitter attenuator making it ideal for use in asynchronous multiplexor systems with gapped transmit clocks. The CS61535A provides a matched, constant impedance output stage to insure signal quality on mismatched, poorly terminated lines. The IC uses a digital Delay-Locked-Loop clock and data recovery circuit which is continuously calibrated from a crystal reference to provide excellent stability and jitter tolerance. * Provides Analog PCM Line Interface for T1 and E1 Applications Clock Recovery Functions * Provides Line Driver, and Data and * Transmit Side Jitter Attenuation * Low Power Consumption (typically 175 mW) Starting at 6 Hz, with > 300 UI of Jitter Tolerance Applications * * * * B8ZS/HDB3/AMI Encoders/Decoders * 14 dB of Transmitter Return Loss * Compatible with SONET, M13 , CCITT G.742, and Other Asynchronous Muxes [ ] = Pin Function in Extended Hardware Mode ( ) = Pin Function in Host Mode XTALIN XTALOUT 9 TCLK TPOS [TDATA] TNEG [TCODE] RCLK RPOS [RDATA] RNEG [BPV] 2 3 4 8 7 6 LOOP BACK AMI, B8ZS, HDB3 CODER 10 Interfacing network transmission equipment such as SONET multiplexor and M13 to a DSX-1 cross connect. Interfacing customer premises equipment to a CSU. Interfacing to E1 links. Ordering Information CS61535A-IL1Z 28 Pin PLCC (Lead-free) CS61535A-IL1 28 Pin PLCC (j-leads) (CLKE) (INT) (SDI) (SDO) MODE TAOS LEN0 LEN1 LEN2 5 28 23 24 PULSE SHAPER 25 TGND 14 TV+ 15 13 JITTER ATTENUATOR CONTROL 16 TTIP CLOCK & DATA RECOVERY TRING LINE DRIVER LINE RECEIVER 19 RTIP 20 RRING 17 MTIP [RCODE] 18 MRING [PCS] 11 DPM [AIS] SIGNAL QUALITY MONITOR 27 1 12 21 22 DRIVER MONITOR 26 RLOOP LLOOP (CS) (SCLK) ACLKI LOS RV+ RGND Crystal Semiconductor Corporation Cirrus Logic, Inc. http://www.cirrus.com P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 Copyright Cirrus Logic, Inc.Semiconductor Corporation 1996 Copyright (c) Crystal 2009 (All Rights Reserved) Rights Reserved) (All MAY '96 JUL '09 DS40F2 DS40F3 1 -XO &21),'(17,$/ ABSOLUTE MAXIMUM RATINGS CS61535A Symbol Min Max Units RV+ 6.0 V TV+ (RV+) + 0.3 V Input Voltage, Any Pin (Note 1) Vin RGND-0.3 (RV+) + 0.3 V Input Current, Any Pin (Note 2) Iin -10 10 mA Ambient Operating Temperature TA -40 85 C Storage Temperature Tstg -65 150 C WARNING:Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V. 2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA. DC Supply Parameter (referenced to RGND,TGND=0V) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Units DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 V Ambient Operating Temperature TA -40 25 85 C Power Consumption (Notes 4, 5) PC 290 350 mW Power Consumption (Notes 4, 6) PC 175 mW Notes: 3. TV+ must not exceed RV+ by more than 0.3V. 4. Power consumption while driving line load over operating temperature range. Includes IC and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF load. 5. Assumes 100% ones density and maximum line length at 5.25V. 6. Assumes 50% ones density and 300ft. line length at 5.0V. 2 DS40F3 -XO &21),'(17,$/ CS61535A DIGITAL CHARACTERISTICS (TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V) Parameter Symbol Min Typ Max High-Level Input Voltage 2.0 Pins 1-4, 17, 18, 23-28 (Notes 7, 8, 9) VIH Low-Level Input Voltage Pins 1-4, 17, 18, 23-28 (Notes 7, 8, 9) VIL 0.8 High-Level Output Voltage (IOUT = -40 A) 4.0 VOH Pins 6-8, 11, 12, 25 (Notes 7, 8, 10) Low-Level Output Voltage (IOUT = 1.6 mA) 0.4 Pins 6-8, 11, 12, 23, 25 (Notes 7, 8, 10) VOL Input Leakage Current (Except Pin 5) 10 Low-Level Input Voltage, Pin 5 VIL 0.2 High-Level Input Voltage, Pin 5 VIH (RV+) - 0.2 Mid-Level Input Voltage, Pin 5 (Note 11) VIM 2.3 2.7 Notes: 7. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40A). 8. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate output. 9. Pins 17 and 18 of the CS61535A are digital inputs in the Extended Hardware Mode. 10. Output drivers will drive CMOS logic levels into a CMOS load. 11. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating. Units V V V V A V V V ANALOG SPECIFICATIONS Parameter (TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V) Min Typ Max Units Jitter Attenuator Jitter Attenuation Curve Corner Frequency (Note 12) 6 Hz T1 Jitter Attenuation in Remote Loopback (Note 13) Jitter Freq. [Hz] Amplitude [UIpp] 10 10 3.0 6.0 dB 100 10 20 30 dB 500 10 35 35 dB 1k 5 40 50 dB 10k, 40k 0.3 40 50 dB E1 Jitter Attenuation in Remote Loopback (Note 14) Jitter Freq. [Hz] Amplitude [UIpp] 10 1.5 3.0 6.0 dB 100 1.5 20 32 dB 400 1.5 30 43 dB 1k 1.5 35 50 dB 10k, 100k 0.2 35 50 dB Attenuator Input Jitter Tolerance (Note 15) 12 23 UI Notes: 12. Not production tested. Parameters guaranteed by design and characterization. 13. Attenuation measured at the demodulator output of an HP3785B with input jitter equal to 3/4 of measured jitter tolerance using a measurement bandwidth of 1 Hz (10 DS40F3 3 -XO &21),'(17,$/ ANALOG SPECIFICATIONS CS61535A (TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V) Parameter Min Typ Max Units Transmitter AMI Output Pulse Amplitudes (Note 16) 2.14 2.37 2.6 V E1, 75 (Note 17) 2.7 3.0 3.3 V E1, 120 (Note 18) 2.7 3.0 3.3 V T1, FCC Part 68 (Note 19) 2.4 3.0 3.6 V T1, DSX-1 (Note 20) E1 Zero (space) level (LEN2/1/0 = 0/0/0) -0.237 0.237 V 75 application (Note 17) -0.3 0.3 V 120 application (Note 18) Recommended Output Load at TTIP and TRING 75 Jitter Added During Remote Loopback (Note 21) 0.005 0.02 UI 10Hz - 8kHz 0.008 0.025 UI 8kHz - 40kHz 0.010 0.025 UI 10Hz - 40kHz 0.015 0.05 UI Broad Band Power in 2kHz band about 772kHz (Notes 12, 16) 12.6 15 17.9 dBm Power in 2kHz band about 1.544MHz (Notes 12, 16) -29 -38 dB (referenced to power in 2kHz band at 772kHz) Positive to Negative Pulse Imbalance (Notes 12, 16) 0.2 0.5 dB T1, DSX-1 -5 5 % E1 amplitude at center of pulse -5 5 % E1 pulse width at 50% of nominal amplitude Transmitter Return Loss (Notes 12, 16, 22) 8 dB 51 kHz to 102 kHz 14 dB 102 kHz to 2.048 MHz 10 dB 2.048 MHz to 3.072 MHz Transmitter Short Circuit Current (Notes 12, 23) 50 mA RMS Notes: 16. Using a 0.47 F capacitor in series with the primary of a transformer recommended in the Applications Section. 17. Amplitude measured at the transformer (CS61535A-1:1 or 1:1.26) output across a 75 load for line length setting LEN2/1/0 = 0/0/0. 18. Amplitude measured at the transformer (CS61535A-1:1.26) output across a 120 load for line length setting LEN2/1/0 = 0/0/0. 19. Amplitude measured at the transformer (CS61535A-1:1.15) output across a 100 load for line length setting LEN2/1/0 = 0/1/0. 20. Amplitude measured across a 100 load at the DSX-1 cross-connect for line length settings LEN2/1/0 = 0/1/1, 1/0/0, 1/0/1, 1/1/0 and 1/1/1 after the length of #22 AWG ABAM equivalent cable specified in Table 3. The CS61535A requires a 1:1.15 transformer. 21. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK. 22. Return loss = 20 log10 ABS((z1 +z0)/(z1-z0)) where z1 = impedance of the transmitter, and z0 = impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0 and a 1:1 transformer terminated with a 75 load, or a 1:1.26 transformer terminated with a 120 load. 23. Measured broadband through a 0.5 resistor across the secondary of a 1:1.26 transformer during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0. 4 DS40F3 -XO &21),'(17,$/ ANALOG SPECIFICATIONS CS61535A (TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V) Min Typ Max Units Parameter Driver Performance Monitor MTIP/MRING Sensitivity: Differential Voltage Required for Detection Receiver RTIP/RRING Input Impedance Sensitivity Below DSX (0dB = 2.4V) Data Decision Threshold T1, DSX-1 T1, DSX-1 T1, FCC Part 68 and E1 Data Decision Threshold -13.6 (Note 24) (Note 25) (Note 26) T1 E1 60 53 45 160 0.60 50k 65 65 50 65 50 175 70 77 55 190 % % % % % V dB of peak of peak of peak of peak of peak bits Allowable Consecutive Zeros before LOS Receiver Input Jitter Tolerance (Note 27) 0.4 UI 10kHz - 100kHz 6.0 UI 2kHz 300 UI 10Hz and below Loss of Signal Threshold (Note 28) 0.25 0.30 0.50 V Notes: 24. For input amplitude of 1.2 Vpk to 4.14 Vpk. 25. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+. 26. For input amplitude of 1.05 Vpk to 3.3 Vpk. 27. Jitter tolerance increases at lower frequencies. See Figure 11. 28. LOS goes high after 160 to 190 consecutive zeros are received. A zero is output on RPOS and RNEG (or RDATA) for each bit period where the input signal amplitude remains below the data decision threshold. The analog input squelch circuit operates when the input signal amplitude above ground on the RTIP and RRING pins falls within the squelch range long enough for the internal slicing threshold to decay within this range. Operation of the squelch causes zeros to be output on RPOS and RNEG as long as the input amplitude remains below 0.25V. During receive LOS, pulses greater than 0.25V in amplitude may be output on RPOS and RNEG. LOS returns low after the ones density reaches 12.5% (based upon 175 bit periods starting with a one and containing less than 100 consecutive zeros) as prescribed in ANSI T1.231-1993. DS40F3 5 -XO &21),'(17,$/ T1 SWITCHING CHARACTERISTICS Parameter Crystal Frequency ACLKI Duty Cycle ACLKI Frequency RCLK Duty Cycle RCLK Cycle Width (Note 29) (Note 30) (Notes 31, 32) (Note 32) CS61535A (TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Symbol fc tpwh3/tpw3 faclki tpwh1/tpw1 tpw1 tpwh1 tpwl1 tr tf tsu2 th2 tsu1 tsu1 tsu1 th1 th1 th1 ftclk tpwh2 Min 40 320 130 100 25 25 150 150 150 150 150 150 80 150 Typ 6.176000 1.544 78 29 648 190 458 274 274 274 274 274 274 1.544 Max 60 980 240 850 85 85 500 500 Units MHz % MHz % % ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns Rise Time, All Digital Outputs (Note 33) Fall Time, All Digital Outputs (Note 33) TPOS/TNEG (TDATA) to TCLK Falling Setup Time TCLK Falling to TPOS/TNEG (TDATA) Hold Time RPOS/RNEG Valid Before RCLK Falling (Note 34) RDATA Valid Before RCLK Falling (Note 35) RPOS/RNEG Valid Before RCLK Rising (Note 31) RPOS/RNEG Valid After RCLK Falling (Note 34) RDATA Valid After RCLK Falling (Note 35) RPOS/RNEG Valid After RCLK Rising (Note 31) TCLK Frequency TCLK Pulse Width (Notes 12, 31, 34, 36, 37) (Notes 35, 36, 37) Notes: 29. Crystal must meet specifications described in Appendix A. 30. ACLKI provided by an external source or TCLK, but not RCLK. 31. Hardware Mode, or Host Mode (CLKE = 0). 32. RCLK cycle width will vary with extent by which pulses displaced by jitter. Specified under worst case jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1. 33. At max load of 1.6 mA and 50 pF. 34. Host Mode (CLKE = 1). 35. Extended Hardware Mode. 36. The maximum TCLK burst rate is 5 MHz and tpw2(min) = 200 ns. The maximum gap size that can be tolerated on TCLK is 12 VI. 37. The transmitted pulse width does not depend on the TCLK duty cycle. tpw1 RCLK t pwl1 t su1 t pwh1 t h1 EXTENDED HARDWARE MODE OR HOST MODE (CLKE = 1) RPOS RNEG RDATA BPV RCLK HARDWARE MODE OR HOST MODE (CLKE = 0) Figure 1. Recovered Clock and Data Switching Characteristics 6 DS40F3 -XO &21),'(17,$/ E1 SWITCHING CHARACTERISTICS Parameter Crystal Frequency ACLKI Duty Cycle ACLKI Frequency RCLK Duty Cycle RCLK Cycle Width (Note 29) (Note 30) (Notes 31, 32) (Note 32) CS61535A (TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Symbol fc tpwh3/tpw3 faclki tpwh1/tpw1 tpw1 tpwh1 tpwl1 tpw1 tpwh1 tpwl1 tr tf tsu2 th2 tsu1 tsu1 tsu1 th1 th1 th1 ftclk tpwh2 Min 40 310 90 120 320 100 25 25 100 100 100 100 100 100 80 150 Typ 8.192000 2.048 29 488 140 348 488 348 140 194 194 194 194 194 194 2.048 Max 60 670 190 500 670 85 85 340 340 Units MHz % MHz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns RCLK Cycle Width (Note 32) Rise Time, All Digital Outputs (Note 33) Fall Time, All Digital Outputs (Note 33) TPOS/TNEG (TDATA) to TCLK Falling Setup Time TCLK Falling to TPOS/TNEG (TDATA) Hold Time RPOS/RNEG Valid Before RCLK Falling (Note 34) RDATA Valid Before RCLK Falling (Note 35) RPOS/RNEG Valid Before RCLK Rising (Note 31) RPOS/RNEG Valid After RCLK Falling (Note 34) RDATA Valid After RCLK Falling (Note 35) RPOS/RNEG Valid After RCLK Rising (Note 31) TCLK Frequency TCLK Pulse Width (Notes 31, 34, 36, 37) (Notes 35, 36, 37) tr 90% 10% 90% tf Any Digital Output 10% Figure 2. Signal Rise and Fall Characteristics t pw2 t pwh2 t pw3 TCLK t su2 TPOS/TNEG t h2 t pwh3 ACLKI Figure 3a. Transmit Clock and Data Switching Characteristics DS40F3 Figure 3b. Alternate External Clock Characteristics 7 -XO &21),'(17,$/ SWITCHING CHARACTERISTICS Inputs: Logic 0 = 0V, Logic 1 = RV+) (TA = -40 to 85C; TV+, RV+ = 5%; CS61535A Parameter Symbol Min Typ Max SDI to SCLK Setup Time tdc 50 SCLK to SDI Hold Time tcdh 50 SCLK Low Time tcl 240 SCLK High Time tch 240 SCLK Rise and Fall Time tr, tf 50 CS to SCLK Setup Time tcc 50 SCLK to CS Hold Time (Note 38) tcch 50 CS Inactive Time tcwh 250 SCLK to SDO Valid (Note 39) tcdv 200 CS to SDO High Z tcdz 100 Input Valid To PCS Falling Setup Time tsu4 50 PCS Rising to Input Invalid Hold Time th4 50 PCS Active Low Time tpcsl 250 Notes: 38. For CLKE = 0, CS must remain low at least 50 ns after the 16th falling edge of SCLK. 39. Output load capacitance = 50pF. Units ns ns ns ns ns ns ns ns ns ns ns ns ns t cwh CS t cc SCLK t dc SDI LSB CONTROL BYTE t cdh LSB DATA BYTE t cdh MSB t ch t cl t cch Figure 4. Serial Port Write Timing Diagram 8 DS40F3 -XO &21),'(17,$/ CS61535A CS t cdz SCLK t cdv SDO CLKE = 1 Figure 5. Serial Port Read Timing Diagram HIGH Z PCS t su4 LEN0/1/2, TAOS, RLOOP, LLOOP, RCODE, TCODE t pcsl VALID INPUT DATA th4 Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram DS40F3 9 -XO &21),'(17,$/ THEORY OF OPERATION Enhancements in CS61535A 7KH &6$ SURYLGHV KLJKHU SHUIRUPDQFH DQG PRUH IHDWXUHV WKDQ WKH &6 LQFOXGLQJ * * * * * * * * ORZHU SRZHU FRQVXPSWLRQ ,QWHUQDOO\ P DWFKHG WUD QVPLWWHU RX WSXW LP SHG DQFH IRU LPSURYHG VLJQDO TXDOLW\ 2SWLRQDO $0, %=6 +'% HQFRGHUGHFRGHU RU H[WHUQDO OLQH FRGLQJ VXSSRUW 5HFHLYHU $,6 XQIUDPHG DOO RQHV GHWHFWLRQ $16, 7 FR PSOLDQW U HFHLYHU / RVV RI 6LJQDO /26 KDQGOLQJ 7UDQVPLWWHU 7 7,3 D QG 7 5,1* R XWSXWV D UH IRUFHG ORZ ZKHQ 7&/. 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Differences in Operating Modes 10 Table 2. Pin Definitions DS40F3 -XO &21),'(17,$/ HARDWARE MODE TAOS LLOOP RLOOP LEN0/1/2 CS61535A CONTROL TPOS TNEG JITTER ATTENUATOR TTIP LINE DRIVER MRING MTIP TRING TRANSMIT TRANSFORMER CS62180B FRAMER CIRCUIT CS61535A RPOS RNEG DRIVER MONITOR DPM RTIP LINE RECEIVER RRING RECEIVE TRANSFORMER EXTENDED HARDWARE MODE TCODE RCODE TAOS LLOOP RLOOP PCS LEN0/1/2 CONTROL TTIP TDATA AMI B8ZS, HDB3, CODER RDATA JITTER ATTENUATOR LINE DRIVER TRING TRANSMIT TRANSFORMER HIGH SPEED MUX (e.g., M13) CS61535A RTIP AIS DETECT LINE RECEIVER RRING RECEIVE TRANSFORMER BPV P SERIAL PORT 5 AIS HOST MODE CLKE CONTROL TPOS TNEG CS62180B FRAMER CIRCUIT RPOS RNEG CONTROL TTIP JITTER ATTENUATOR LINE DRIVER MRING MTIP TRING TRANSMIT TRANSFORMER CS61535A DRIVER MONITOR DPM RTIP LINE RECEIVER RRING RECEIVE TRANSFORMER Figure 7. Overview of Operating Modes DS40F3 11 -XO &21),'(17,$/ LEN2 LEN1 LEN0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 OPTION SELECTED 0-133 FEET 133-266 FEET 266-399 FEET 399-533 FEET 533-655 FEET AT&T CB113 (CS61535A only) CCITT G.703 FCC Part 68, Option A ANSI T1.403 APPLICATION DSX-1 ABAM (AT&T 600B or 600C) CS61535A ZLGWK ZLO O PHH W W KH * SXOVH V KDSH W HPSODWH VKRZQ LQ )LJXUH DQG VSHFLILHG LQ 7DEOH )RU ( D SSOLFDWLRQV WK H & 6$ G ULYHU SUR YLGHV G% RI UHWXUQ ORVV GXULQJ WKH WUDQVPLVVLRQ RI ERW K PDUNV DQ G V SDFHV 7 KLV LPSURYHV V LJQDO TXDOLW\ E\ P LQLPL]LQJ U HIOHFWLRQV R II W KH W UDQV PLWWHU 6LPLODU O HYHOV R I UHW XUQ ORVV DUH SUR YLGHG IRU 7 DSSOLFDWLRQV 7KH &6 $ WU DQVPLWWHU Z LOO GHWHFW D IDLOHG 7&/. DQG ZLOO IRUFH WK H 77 ,3 DQ G 75 ,1* RXW SXWV ORZ NORMALIZED AMPLITUDE 1.0 REPEATER 2.048 MHz E1 CSU NETWORK INTERFACE Table 3. Line Length Selection &6$ OLQH GULYHU LV GHVLJQHG WR GULYH D HTXLYDOHQW ORDG )RU 7 '6; DSSOLFDWLRQV OLQH OHQJWKV IURP WR IHHW DV PHDVXUHG IURP WKH WUDQVPLWWHU WR WKH '6; F URVV F RQQHFW DU H V HOHFWDEOH 7KH I LYH SDUWLWLRQ D UUDQJHPHQW P HHWV $16, 7 UHTXLUHPHQWV ZKHQ XVLQJ $%$0 FD EOH $ W\SLFDO RXWSXW SX OVH LV V KRZQ LQ )L JXUH 7 KHVH SX OVH VHWWLQJV FDQ DOVR EH XV HG WR P HHW && ,77 SX OVH VKDSH UHTXLUHPHQWV IRU 0+] RSHUDWLRQ )RU 7 1HWZRUN ,QWHUIDFH DSSOLFDWLRQV DGGLWLRQDO RSWLRQV DUH SURYLGHG 1RWH WKDW WKH RSWLPDO SXOVH ZLGWK IRU 3D UW QV LV QD UURZHU WKDQ WKH RSWLPDO SX OVH Z LGWK I RU ' 6; Q V 7 KH &6$ DXW RPDWLFDOO\ DG MXVWV WKH SXOVH ZLGW K EDVHG XSRQ WKH OLQH OHQJWK VHOHFWLRQ PDGH 7KH ( * SXOVH VKDSH LV VXSSRUWHG ZLWK OLQH OHQJWK V HOHFWLRQ / (1 7 KH S XOVH AT&T CB 119 SPECIFICATION 0.5 0 CS61535A OUTPUT PULSE SHAPE -0.5 0 250 750 500 TIME (nanoseconds) 1000 Figure 8. Typical Pulse Shape at DSX-1 Cross Connect F or c o axi al cab le , For shielded twisted 75 loa d a nd pair, 120 load and transformer specified transformer specified in Application Section. in Application Section. 2.37 V 3V 0 0.237 V 0 0.30 V 244 ns Nominal peak voltage of a mark (pulse) Peak voltage of a space (no pulse) Nominal pulse width Ratio of the amplitudes of positive and negative 0.95 to 1.05* pulses at the center of the pulse interval Ratio of the widths of positive and negative 0.95 to 1.05* pulses at the nominal half amplitude * When configured with a 0.47 F nonpolarized capacitor in series with the TX transformer primary as shown in Figures A1, A2 and A3. Table 4. CCITT G.703 Specifications 12 DS40F3 -XO &21),'(17,$/ Percent of nominal peak voltage 120 110 100 90 80 244 ns 194 ns Attenuation in dB CS61535A 0 a) Minimum Attenuation Limit 10 20 30 40 50 60 AT&T 62411 Requirements 269 ns b) Maximum Attenuation Limit Measured Performance 50 1 10 100 1k 10 k Frequency in Hz Figure 10. Typical Jitter Attenuation Curve 10 0 -10 -20 219 ns 488 ns Nominal Pulse WDO WR V HW LW V R VFLOODWLRQ IUHTXHQF\ WR W KH DYHUDJH RI WKH 7& /. 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Receiver Block Diagram 7&/. IUHTXHQF\ GXH W R D OORZDEOH 7 &/. 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Selection of Encoder/Decoder Alarm Indication Signal ,Q ([WHQGHG +DUGZDUH 0RGH WKH UHFHLYHU VHWV WKH RXWSXW S LQ $,6 KL JK ZKH Q OHV V WKDQ ]HURV DUH GHWHFWHG RXW RI ELW SHULRGV $,6 UHWXUQV ORZ ZKHQ RU PRUH ]H URV DUH GHW HFWHG RX W RI ELWV Parallel Chip Select ,Q ([WHQGHG +DUGZDUH 0RGH 3&6 FDQ EH XVHG WR JDWH WKH GLJLWDO FRQWURO LQSXWV 7&2'( 5&2'( /(1 / (1 / (1 5 /223 / /223 DQG 7$26 , QSXWV DU H DFFHSWHG RQ WKHV H SLQV RQO\ ZKHQ 3&6 LV ORZ &KDQJHV LQ LQSXWV ZLOO LPPHGL DWHO\ FKDQJH WKH RSHUDWLQJ V WDWH RI WKH GHYLFH 7KHUHIRUH ZKHQ F\FOLQJ 3&6 WR XSGDWH WKH RSHU DWLQJ V WDWH WKH GLJ LWDO FR QWURO LQS XWV V KRXOG E H VWDEOH IRU WKH HQWLUH 3&6 ORZ SHULRG 7KH FRQWURO LQSXWV DUH LJQRUHG ZKHQ 3&6 LV KLJK Power On Reset / Reset 8SRQ SRZHUXS WKH &6$ LV KHOG LQ D VWDWLF VWDWH X QWLO WK H V XSSO\ F URVVHV D WKUH VKROG RI DS DS40F3 17 -XO &21),'(17,$/ CS SCLK SDI CS61535A R/W 0 0 0 0 1 0 0 D0 D0 D1 D1 Address/Command Byte SDO D2 D3 D4 D5 Data Input/Output D2 D3 D4 D5 D6 D6 D7 D7 Figure 13. Input/Output Timing SUR[LPDWHO\ WKUH H 9ROWV : KHQ W KLV WK UHVKROG LV FURVVHG W KH GHYLFH Z LOO GH OD\ I RU DE RXW PV W R DOORZ WKH SRZHU VXSSO\ WR UHDFK RSHUDWLQJ YROWDJH $IWHU WKLV GHOD\ FDOLEUDWLRQ RI WKH GHOD\ OLQHV XVHG LQ WKH WU DQVPLW DQ G U HFHLYH VHFW LRQV FR PPHQFHV 7KH GHOD\ OLQ HV FDQ EH FDO LEUDWHG RQ O\ LI D U HIHU HQFH FORFN LV S UHVHQW 7KH U HIHUHQFH FORFN IRU WKH UHFHLYHU LV SURYLGHG E\ $ &/., RU E\ WKH FU\VWDO RVFLOODWRU LI $&/., LV QRW SUHVHQW 7KH UHIHUHQFH FORFN IRU WKH WUDQVPLWWHU LV SURYLGHG E\ 7&/. 7KH LQLWLDO FDOLEUDWLRQ VKRXOG WDNH OHVV WKDQ PV ,Q RSHUDWLRQ WKH GHOD\ OLQHV DUH FRQWLQXRXVO\ FDOL EUDWHG P DNLQJ WK H SH UIRUPDQFH R I W KH G HYLFH LQGHSHQGHQW RI SRZHU VXSSO\ RU WHPSHUDWXUH YDUL DWLRQV 7 KH FRQWLQXRXV FDOLEUDWLRQ IX QFWLRQ IRUHJRHV D Q\ UH TXLUHPHQW WR UH VHW WK H OLQ H LQW HU IDFH ZKHQ LQ RSHUDWLRQ +RZHYHU D UHVHW IXQFWLRQ LV DYDLODEOH ZKLFK ZLOO FOHDU DOO UHJLVWHUV ,Q WKH +DUGZDUH DQG ([WHQGHG +DUGZDUH PRGHV D UHVHW UHTXHVW LV PDGH E\ VLPXOWDQHRXVO\ VHWWLQJ ERWK 5/223 DQG //223 KLJK IRU DW OHDVW QV 5HVHW ZLOO LQLWLDWH RQ WKH I DOOLQJ HGJH RI WKH UHV HW UHTXHVW IDOOLQJ HGJH RI 5/ 223 DQG / /223 ,Q WKH +RV W 0RGH D UHV HW LV LQLWLDWHG E\ VLPXOWDQHRXVO\ ZULWLQJ 5/223 DQG //223 WR WKH UHJLVWHU ,Q HLWKHU PRGH D UHVHW ZLOO VHW DOO UHJLVWHUV WR DQG VHW /26 KLJK Serial Interface ,Q WKH +RVW 0RGH SLQV WKURXJK VHUYH DV D PLFURSURFHVVRUPLFURFRQWUROOHU LQWHU IDFH 2QH HLJKWELW UHJLVWHU FDQ EH ZULWWHQ WR YLD WKH 6', SLQ RU UHDG IURP WKH 6'2 S LQ DW WKH FORFN UDWH GHWHU PLQHG E\ 6&/ . 7 KURXJK WKLV UHJLV WHU D KRV W FRQWUROOHU FDQ EH XVHG WR FRQWURO RSHUDWLRQDO FKDU 18 DFWHULVWLFV DQG P RQLWRU GHYLFH VW DWXV 7 KH V HULDO SRUW UHD GZULWH WL PLQJ LV LQG HSHQGHQW RI WKH V \V WHP WUDQVPLW DQG UHFHLYH WLPLQJ 'DWD WUDQVIHUV DUH LQLWLDWHG E\ WDNLQJ WKH FKLS VH OHFW L QSXW &6 O RZ &6 PXVW LQ LWLDOO\ E H K LJK 6&/. PD\ E H H LWKHU KL JK R U ORZ ZK HQ &6 L Q LWLDOO\ JRH V O RZ $GG UHVV D QG L QSXW GD WD E LWV DUH FORFNHG LQ RQ W KH UL VLQJ H GJH RI 6&/ . 'DWD RQ 6'2 LV YD OLG DQG V WDEOH RQ WKH IDOO LQJ HGJ H RI 6&/. ZKHQ &/.( LV ORZ DQG RQ WKH ULVLQJ HGJH RI 6&/. ZKHQ &/.( LV KLJ K 'DWD WUDQVIHUV DUH WHUPLQDWHG E\ V HWWLQJ &6 K LJK &6 PD\ J R KL JK QR VRRQHU WKDQ QV DIWHU WKH ULV LQJ HGJH RI WKH 6&/. F \FOH FR UUHVSRQGLQJ WR WKH ODV W ZULW H ELW )RU D VHULDO GD WD UHDG &6 PD\ JR KLJK DQ\ WLPH WR WHUPLQDWH WKH RXWSXW )LJXUH V KRZV WKH WLPLQJ UHODWLRQVKLSV IRU GD WD WUDQVIHUV ZKHQ &/.( :KHQ &/.( GDWD RXWSXW IURP WKH VHULDO SRUW 6'2 LV Y DOLG R Q W KH IDOOLQJ HGJH RI 6&/. )RU &/.( GDWD ELW ' LV KHOG WR WKH IDOOLQJ HGJH RI WKH WK FORFN F\FOH IRU & /.( G DWD EL W ' LV K HOG WR WK H UL VLQJ HGJH RI WK H WK FORFN F\FOH 6'2 JRHV WR D KL JK Read/Write Select; 0 = write, 1 = read LSB of address, Must be 0 Must be 0 Must be 0 Must be 0 Must be 1 Reserved - Must be 0 LSB, first bit 0 1 2 3 4 5 6 R/W ADD0 ADD1 ADD2 ADD3 ADD4 - Table 7. Address/Command Byte DS40F3 -XO &21),'(17,$/ LPSHGDQFH VWDWH HLWKHU DIWHU ELW ' LV RXWSXW RU DW WKH HQG RI WKH KROG SHULRG RI GDWD ELW ' $Q D GGUHVVFRPPDQG E\W H V KRZQ L Q 7 DEOH SUHFHGHV D GDWD UHJLVWHU 7 KH I LUVW EL W RI WKH DG GUHVVFRPPDQG E \WH GH WHUPLQHV Z KHWKHU D U HDG RU D ZU LWH LV U HTXHVWHG 7K H QH[W VL[ ELW V FRQ WDLQ WKH DGG UHVV 7 KH &6 $ UHVSRQGV WR DGGUHVV 7KH ODVW ELW LV LJQRUHG 7KH GDWD UHJLVWHU VKRZQ LQ 7DEOH FDQ EH ZULW WHQ WR WKH VHULDO S RUW 'DWD L V LQSXW RQ WK H H LJKW FORFN F\F OHV L PPHGLDWHO\ I ROORZLQJ WK H DG GUHVVFRPPDQG E\WH %LWV DQG DU H XV HG WR FOHDU DQ LQW HUUXSW LVVXHG IURP WKH ,17 SLQ ZKLFK RFFXUV LQ UHVSRQVH WR D ORVV RI VLJQDO RU D SUREOHP ZLWK WKH RXWSXW GUL YHU ,I ELWV RU DUH WUX H WKH FRUUHVSRQGLQJ LQWHUUXSW LV VXSSUHVVHG 6R LI D ORVV RI VLJQDO LQWHUUXSW LV FOHDUHG E\ ZULWLQJ D W R ELW WKH LQWHUUXSW ZLOO EH UHHQDEOHG E\ ZULWLQJ D WR ELW 7KLV KROGV IRU '30 DV ZHOO 0 1 2 3 4 5 6 MSB: last bit in 7 LSB: first bit in clr LOS clr DPM LEN0 LEN1 LEN2 RLOOP LLOOP TAOS Clear Loss of Signal Clear Driver Performance Monitor Bit 0 - Line Length Select Bit 1 - Line Length Select Bit 2 - Line Lenght Select Remote Loopback Local Loopback Transmit All Ones Select LSB: first bit in 0 1 2 3 4 LOS DPM LEN0 LEN1 LEN2 CS61535A Loss of Signal Driver Performance Monitor Bit 0 - Line Length Select Bit 1 - Line Length Select Bit 2 - Line Lenght Select Table 9. Output Data Bits 0 - 4 Bits 567 Status Reset has occurred or no program input. TAOS in effect. LLOOP in effect. TAOS/LLOOP in effect. RLOOP in effect DPM changed state since last "clear DPM" occured. LOS changed state since last "clear LOS" occured. LOS and DPM have changed state since last "clear LOS" and "clear DPM". Table 10. Coding for Serial Output Bits 5, 6, 7 :ULWLQJ D WR HLWKHU &OHDU /26 RU & OHDU '30 H QDEOHV W KH F RUUHVSRQGLQJ L QWHUUXSW I RU /26 RU '30 2XWSXW GDWD IURP WKH VHULDO LQWHUIDFH LV SUHVHQWHG DV VKRZQ LQ 7DEOHV DQG %LWV DQG FDQ EH UHDG W R YHULI\ O LQH OH QJWK V HOHFWLRQ %LWV DQG PXV W EH GH FRGHG &RGHV DQG ELWV DQ G LQ GLFDWH / 26 DQ G ' 30 V WDWH FKDQJHV :ULWLQJ D WR WKH &OHDU /26 DQGRU &OHDU '30 ELWV LQ WKH UHJLVWHU DOVR UHVHWV VWDWXV ELWV DQG 6'2 JRHV WR D KL JK LPSHGDQFH VWDWH ZKHQ QRW LQ XVH 6'2 DQG 6', PD\ EH WLHG WRJHWKHU LQ DSSOL FDWLRQV Z KHUH W KH KRVW S URFHVVRU KDV D ELGLUHFWLRQDO ,2 SRUW Table 8. Input Data Register :ULWLQJ D WR HLWKHU &OHDU / 26 RU &OHDU '30 RYHU WKH VHULDO LQWHUIDFH KDV WKUHH HIIHFWV WKH F XUUHQW L QWHUUXSW RQ WK H VH ULDO LQWHUIDFH ZLOO EH FOH DUHG 1RWH W KDW VL PSO\ U HDGLQJ WK H UHJLVWHU ELWV ZLOO QRW FOHDU WKH LQWHUUXSW RXWSXW GDWD ELWV D QG ZLOO EH UHVHW DV DSSURSULDWH IXWXUH LQWHUUXSWV IRU W KH FRUUHVSRQGLQJ /26 RU '30 ZLOO EH SUHYHQWHG IURP RFFXULQJ DS40F3 19 -XO &21),'(17,$/ Power Supply 7KH GHYLFH RSHUDWHV IURP D VLQJOH 9ROW VXSSO\ 6HSDUDWH SL QV I RU WU DQVPLW DQ G U HFHLYH V XSSOLHV SURYLGH LQ WHUQDO L VRODWLRQ 7 KHVH SL QV VKRXOG EH FRQQHFWHG H[W HUQDOO\ QHDU WK H GHY LFH DQG GHFRX SOHG WR WKHLU UH VSHFWLYH JUR XQGV 7 9 PXVW QR W H[FHHG 59 E\ PRUH WKDQ 9 'HFRXSOLQJ DQG ILOWHULQJ RI WKH SRZHU VXSSOLHV LV FUXFLDO IRU WKH SURSHU RSHUDWLRQ RI WKH DQDORJ FLU FXLWV LQ ERWK WKH WUDQVPLW DQG UHFHLYH SDWKV $ ) FDSDFLWRU VKRXOG E H F RQQHFWHG EHWZHHQ 7 9 DQG 7*1' DQG D ) FDSDFLWRU VKRXOG EH FRQ QHFWHG EHW ZHHQ 59 DQG 5*1' 8VH P \ODU RU FHUDPLF F DSDFLWRUV DQG SOD FH W KHP DV FOR VHO\ DV SRVVLEOH WR WKHLU UHVSHFWLYH SRZHU VXSSO\ SLQV $ ) WD QWDOXP FD SDFLWRU VKRXOG EH DGG HG FO RVH WR W KH 5 95*1' V XSSO\ : LUH ZU DS EU HDG ERDUGLQJ RI WKH OLQH LQWHUIDFH LV QRW UHFRPPHQGHG EHFDXVH O HDG U HVLVWDQFH D QG LQGXFWDQFH V HUYH W R GHIHDW WKH IXQFWLRQ RI WKH GHFRXSOLQJ FDSDFLWRUV CS61535A Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. Call: (512) 445-7222 20 DS40F3 -XO &21),'(17,$/ PIN DESCRIPTIONS Hardware Mode ACLKI 1 TAOS +DUGZDUH 0RGH 3LQRXW 28 TCLK 2 LLOOP 27 TPOS 3 RLOOP 26 TNEG 4 LEN2 25 MODE 5 LEN1 24 RNEG 6 LEN0 23 RPOS 7 RGND 22 RCLK 8 RV+ 21 XTALIN 9 RRING 20 XTALOUT 10 RTIP 19 18 DPM 11 MRING 17 LOS 12 MTIP 16 TTIP 13 TRING 15 TGND 14 TV+ CS61535A ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT DPM LOS TTIP TGND 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view 4 3 2 1 28 27 26 25 24 23 22 21 20 19 TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP MRING MTIP TRING TV+ DS40F3 21 -XO &21),'(17,$/ CS61535A Extended Hardware Mode ([WHQGHG +DUGZDUH 0RGH 3LQRXW ACLKI TCLK TDATA TCODE MODE BPV RDATA RCLK XTALIN XTALOUT AIS LOS TTIP TGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP PCS RCODE TRING TV+ ACLKI TCLK TDATA TCODE MODE BPV RDATA RCLK XTALIN XTALOUT AIS LOS TTIP TGND 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view 4 3 2 1 28 27 26 25 24 23 22 21 20 19 TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP PCS RCODE TRING TV+ 22 DS40F3 -XO &21),'(17,$/ CS61535A Host Mode ACLKI 1 0RGH 28 CLKE +RVW 3LQRXW TCLK 2 SCLK 27 TPOS 3 CS 26 TNEG 4 SDO 25 MODE 5 SDI 24 RNEG 6 INT 23 RPOS 7 RGND 22 RCLK 8 RV+ 21 XTALIN 9 RRING 20 XTALOUT 10 RTIP 19 18 DPM 11 MRING 17 LOS 12 MTIP 16 TTIP 13 TRING 15 TGND 14 TV+ ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT DPM LOS TTIP TGND 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view 4 3 2 1 28 27 26 25 24 23 22 21 20 19 CLKE SCLK CS SDO SDI INT RGND RV+ RRING RTIP MRING MTIP TRING TV+ DS40F3 23 -XO &21),'(17,$/ Power Supplies RGND - Ground, Pin 22. 3RZHU VXSSO\ JURXQG IRU DOO VXEFLUFXLWV H[FHSW WKH WUDQVPLW GULYHU W\SLFDOO\ 9ROWV RV+ - Power Supply, Pin 21. 3RZHU VXSSO\ IRU DOO VXEFLUFXLWV H[FHSW WKH WUDQVPLW GULYHU W\SLFDOO\ 9ROWV TGND - Ground, Transmit Driver, Pin 14. 3RZHU VXSSO\ JURXQG IRU WKH WUDQVPLW GULYHU W\SLFDOO\ 9ROWV CS61535A TV+ - Power Supply, Transmit Driver, Pin 15. 3RZHU VXSSO\ IRU WKH WUDQVPLW GULYHU W\SLFDOO\ 9ROWV 79 PXVW QRW H[FHHG 59 E\ PRUH WKDQ 9 Oscillator XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10. $ 0+] RU 0+] FU\VWDO VKRXOG EH FRQQHFWHG DFURVV WKHVH SLQV ,I D 0+] RU 0+] FO RFN LV SURYLGHG RQ $&/., SLQ WKH MLWWHU DWWHQXDWRU PD\ EH GLVDEOHG E\ W\LQJ ;7$/,1 3LQ WR 59 WKURXJK D N UHVLVWRU DQG IORDWLQJ ;7$/287 3LQ 2YHUGULYLQJ WKH RVFLOODWRU ZLWK DQ H[WHUQDO FORFN LV QRW VXSSRUWHG See Appendix A for crystal specifications. Control ACLKI - Alternate External Clock Input, Pin 1. 7KH &6$ GRHV QRW UHTXLUH D FORFN VLJQDO WR EH LQSXW RQ $&/., ZKHQ D FU\VWDO LV FRQQHFWHG EHWZHHQ S LQV DQ G ,I D FOR FN L V Q RW S URYLGHG RQ $& /., WK LV LQS XW PXV W E H JUR XQGHG ,I $&/., LV JURXQGHG WKH RVFLOODWRU LQ WKH MLWWHU DWWHQXDWRU LV XVHG WR FDOLEUDWH WKH FORFN UHFRYHU\ FLUFXLW DQG 7$26 LV QRW DYDLODEOH CLKE - Clock Edge, Pin 28. (Host Mode) 6HWWLQJ &/.( WR ORJ LF FDXVHV 5326 DQG 51(* WR EH YDO LG RQ WKH IDOOLQJ HGJH RI 5&/. DQG 6'2 WR EH YDOLG RQ WKH ULVLQJ HGJH RI 6&/. &RQYHUVHO\ VHWWLQJ &/.( WR ORJLF FDXVHV 5326 DQG 51(* WR EH YDO LG RQ WKH ULVLQJ HGJH RI 5&/. DQG 6'2 WR EH YDO LG RQ WKH IDOOLQJ HGJH RI 6&/. CS - Chip Select, Pin 26. (Host Mode) 7KLV SLQ PXVW WUDQVLWLRQ IURP KLJK WR ORZ WR UHDG RU ZULWH WKH VHULDO SRUW INT - Receive Alarm Interrupt, Pin 23. (Host Mode) *RHV ORZ ZKHQ /26 RU '30 FKD QJH VWDWH WR IODJ WKH KRVW SURFHVVRU ,17 LV FOHDUHG E\ ZULWLQJ &OHDU /26 RU &OHDU '30 WR WKH UHJLVWHU ,17 LV DQ R SHQ GUDLQ RXWSXW DQG VKRXOG EH WLHG WR WKH SRZHU VXSSO\ WKURXJK D UHVLVWRU 24 DS40F3 -XO &21),'(17,$/ CS61535A LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended Hardware Modes) 'HWHUPLQHV WKH VKDSH DQG DPSOLWXGH RI WKH WUDQVPLWWHG SXOVH WR DFFRPPRGDWH VHYHUDO FDEOH W\SHV DQG OHQ JWKV 6HH 7 DEOH IRU LQIR UPDWLRQ RQ OLQ H OHQJWK V HOHFWLRQ $OVR FRQ WUROV WKH UHFHLYHU VOLFLQJ OHYHO DQG WKH OLQH FRGH LQ ([WHQGHG +DUGZDUH 0RGH LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes) 6HWWLQJ //223 WR D ORJLF URXWHV WKH WUDQVPLW FORFN DQG GDWD WKURXJK WR W KH UHFHLYH FORFN DQG GDWD SLQV 732671(* RU 7'$7$ DUH VWLOO WUDQVPLWWHG XQOHVV RYHUULGGHQ E\ D 7$26 UHTXHVW ,QSXWV RQ 57,3 DQG 55,1* DUH LJQRUHG MODE - Mode Select, Pin 5. 'ULYLQJ W KH 02'( S LQ KLJK S XWV W KH &6$ OL QH LQWHUIDFH L Q W KH +RVW 0R GH ,Q WK H K RVW PRGH D VHULDO FRQWURO SRUW LV XVHG WR FRQWURO WKH &6$ OLQH LQWHUIDFH DQG GHWHUPLQH LWV VWDWXV *URXQGLQJ WKH 02 '( SLQ SXW V WKH &6 $ OL QH L QWHUIDFH LQ WKH +D UGZDUH 0 RGH Z KHUH FRQILJXUDWLRQ DQG VWDWXV DUH FRQWUROOHG E\ GLVFUHWH SLQV )ORDWLQJ WKH 02'( SLQ RU GULYLQJ LW WR 9 SX WV WK H & 6$ LQ ([WHQGHG +DU GZDUH 0R GH ZKH UH FR QILJXUDWLRQ DQG VW DWXV D UH FRQWUROOHG E\ GL VFUHWH SLQV :KHQ IORD WLQJ 02'( WKH UH VKRXOG EH QR H[W HUQDO ORDG RQ WKH SLQ 02'( GHILQHV WKH VWDWXV RI SLQV VHH 7DEOH PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode) 6HWWLQJ 3&6 K LJK FDX VHV W KH & 6$ O LQH LQW HUIDFH WR LJQ RUH W KH 7&2'( 5&2'( / (1 /(1 /(1 5/223 //223 DQG 7$26 LQSXWV RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode) 6HWWLQJ 5&2'( O RZ HQ DEOHV %= 6 RU +'% ]H UR V XEVWLWXWLRQ LQ W KH UHF HLYHU GHF RGHU 6HW WLQJ 5&2'( KLJK HQDEOHV WKH $0, UHFHLYHU GHFRGHU VHH 7DEOH RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes) 6HWWLQJ 5/ 223 WR D OR JLF FDXVHV WKH UHFRYHUHG FORFN DQG GDWD WR EH V HQW WKUR XJK WKH MLWWHU DWWHQXDWRU LI DFWLYH DQG WKURXJK WKH GULYHU EDFN WR WKH OLQH 7KH UHFRYHUHG VLJQDO LV DOVR VHQW WR 5&/. DQG 532651(* RU 5'$7$ $Q\ 7$26 UHTXHVW LV LJQRUHG 6LPXOWDQHRXVO\ WDNLQJ 5/223 DQG //223 KLJK IRU DW OHDVW QV LQLWLDWHV D GHYLFH UHVHW SCLK - Serial Clock, Pin 27. (Host Mode) &ORFN XVHG WR UHDG RU ZULWH WKH VHULDO SRUW UHJLVWHUV 6&/. FDQ EH HLWKHU KLJK RU ORZ ZKHQ WKH OLQH LQWHUIDFH LV VHOHFWHG XVLQJ WKH &6 SLQ SDI - Serial Data Input, Pin 24. (Host Mode) 'DWD IRU WKH RQFKLS UHJLVWHU 6DPSOHG RQ WKH ULVLQJ HGJH RI 6&/. SDO - Serial Data Output, Pin 25. (Host Mode) 6WDWXV DQ G FR QWURO LQIR UPDWLRQ IURP WKH RQ FKLS UHJL VWHU ,I &/ .( LV KL JK 6'2 LV YDOLG RQ WK H ULVLQJ HGJH RI 6&/. ,I &/.( LV ORZ 6'2 LV YDOLG RQ WKH IDOOLQJ HGJH RI 6&/. 7KLV SLQ JRHV WR D KLJKLPSHGDQFH VWDWH ZKHQ WKH VHULDO SRUW LV EHLQJ ZULWWHQ WR RU DIWHU ELW ' LV RXWSXW DS40F3 25 -XO &21),'(17,$/ CS61535A TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes) 6HWWLQJ 7$26 WR D ORJLF FDXVHV FRQWLQXRXV RQHV WR EH WUDQVPLWWHG DW WKH IUHTXHQF\ GHWHUPLQHG E\ $&/., TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode) 6HWWLQJ 7&2'( ORZ HQDEOHV %=6 RU +'% ]H UR VXEVWLWXWLRQ LQ WKH WUDQVPLWWHU HQFRGHU 6HWWLQJ 7&2'( KLJK HQDEOHV WKH $0, WUDQVPLWWHU HQFRGHU Data RCLK - Recovered Clock, Pin 8. 7KH UHFHLYHU UHFRYHUHG FORFN LV RXWSXW RQ WKLV SLQ RDATA - Receive Data - Pin 7. (Extended Hardware Mode) 'DWD UHFRYHUHG IURP WKH 57,3 DQG 55,1* LQSXWV LV RXWSXW DW WKLV SLQ DIWHU EHLQJ GHFRGHG E\ WKH OLQH FRGH GHFRGHU 5'$7$ LV 15= 5'$7$ LV VWDEOH DQG YDOLG RQ WKH IDOOLQJ HGJH RI 5&/. RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host Modes) 7KH UHFHLYHU UHFRYHUHG 15= GLJLWDO GDWD LV RXWSXW RQ WKHVH SLQV ,Q WKH +DUGZDUH 0RGH 5326 DQG 51(* DUH VWDEOH DQG YDOLG RQ WKH ULVLQJ HGJH RI 5&/. ,Q WKH +RVW 0RGH &/.( GHWHUPLQHV WKH FOR FN HG JH IRU ZKL FK 5326 DQ G 51( * DUH VWDEOH DQG YDOLG 6HH 7DEOH $ SRV LWLYH SXOVH ZLWK UHV SHFW W R JURX QG UHF HLYHG RQ WKH 57,3 SLQ JHQHUDWHV D OR JLF RQ 5326 DQG D SR VLWLYH SXOVH UHFHLYHG RQ WKH 55,1* SLQ JHQHUDWHV D ORJLF RQ 51(* RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20. 7KH $0, UHF HLYH V LJQDO LV L QSXW W R W KHVH SLQV $ FHQWHUWDSSHG FH QWHUJURXQGHG VWHSXS WUDQVIRUPHU LV UHTXLUHG RQ WKHVH LQSXWV DV VKRZQ LQ )LJ XUH $ LQ WKH Applications VHFWLRQ 'DWD DQG FORFN DUH UHFRYHUHG DQG RXWSXW RQ 5&/. DQG 532651(* RU 5'$7$ TCLK - Transmit Clock, Pin 2. 7KH 0+] RU 0+] WUDQVPLW FORFN LV LQSXW RQ WKLV SLQ 732671(* RU 7 '$7$ DUH VDPSOHG RQ WKH IDOOLQJ HGJH RI 7&/. TDATA - Transmit Data, Pin 3. (Extended Hardware Mode) 7UDQVPLWWHU 15= LQSXW GDWD ZKLFK SDVVHV WKURXJK WKH OLQH FRGH HQFRGHU DQG LV WKHQ GULYHQ RQ WR WKH OLQH WKURXJK 77,3 DQG 75,1* 7'$7$ LV VDPSOHG RQ WKH IDOOLQJ HGJH RI 7&/. TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and Host Modes) ,QSXWV IRU FORFN DQG GDWD WR EH WUDQVPLWWHG 7KH VLJQDO LV GULYHQ RQ W R WKH OLQH WKURXJK 77,3 DQG 75,1* 7 326 D QG 71(* D UH V DPSOHG RQ WKH IDO OLQJ H GJH RI 7&/. $ 7326 LQSXW FDXVHV D SRVLWLYH SXOVH WR EH WUDQVPLWWHG ZKLOH D 71(* LQSXW FDXVHV D QHJDWLYH SXOVH WR EH WUDQVPLWWHG TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. 7KH $0, VLJQDO LV GULYHQ WR WKH OLQH WKURXJK WKHVH SLQV ,Q WKH &6$ WKLV RXWSXW LV GHVLJQHG WR GULYH D ORDG $ RU WUDQVIRUPHU LV UHTXLUHG DV VKRZQ LQ )LJXUH $ 26 DS40F3 -XO &21),'(17,$/ Status CS61535A AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode) $,6 J RHV K LJK ZK HQ X QIUDPHG D OORQHV F RQGLWLRQ E OXH D ODUP L V G HWHFWHG X VLQJ WKH G HWHFWLRQ FULWHULD RI OHVV WKDQ WKUHH ]HURV RXW RI ELW SHULRGV BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode) %39 VWUREHV KLJK ZKHQ D ELSRODU YLRODWLRQ LV GHWHFWHG LQ WKH UHFHLYHG VLJQDO %=6 RU +'% ]HUR VXEVWLWXWLRQV DUH QRW IODJJHG DV ELSRODU YLRODWLRQV LI WKH %=6 RU +'% GHFRGHU KDV EHHQ HQDEOHG DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes) '30 JRHV KLJK LI QR DFWLYLW\ LV GHWHFWHG RQ 07,3 DQG 05,1* LOS - Loss of Signal, Pin 12. /26 JRHV KLJK ZKHQ FRQVHFXWLYH ]HURV KDYH EHHQ UHFHLYHG )RU WKH &6$ /26 UHWXUQV ORZ Z KHQ WKH RQH V G HQVLW\ U HDFKHV EDVHG X SRQ ELW SHULRGV VWDUWLQJ Z LWK D RQH DQ G FRQWDLQLQJ OHVV WKDQ FRQVHFXWLYH ]HURV DV SUHVFULEHG E\ $16, 7 MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes) 7KHVH SLQV DUH QRUPDOO\ FRQQHFWHG WR 77,3 DQG 75,1* DQG PRQLWRU WKH RXWSXW RI D &6$ ,I WKH ,17 SLQ LQ WKH KRVW PRGH LV XVHG DQG WKH PRQLWRU LV QRW XVHG ZULWLQJ &OHDU '30 WR WKH VHULDO LQWHUIDFH ZLOO SUHYHQW DQ LQWHUUXSW IURP WKH GULYHU SHUIRUPDQFH PRQLWRU DS40F3 27 -XO &21),'(17,$/ CS61535A 28 15 E1 1 14 28 pin Plastic DIP D A A1 e1 B L SEATING PLANE B1 C eA NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX 3.94 4.32 5.08 0.155 0.170 0.200 A A1 0.51 0.76 1.02 0.020 0.030 0.040 B 0.36 0.46 0.56 0.014 0.018 0.022 B1 1.02 1.27 1.65 0.040 0.050 0.065 0.20 0.25 0.38 0.008 0.010 0.015 C 36.45 36.83 37.21 1.435 1.450 1.465 D E1 13.72 13.97 14.22 0.540 0.550 0.560 e1 2.41 2.54 2.67 0.095 0.100 0.105 eA 15.24 15.87 0.600 0.625 L 3.18 0.150 3.81 0.125 0 15 15 0 28-pin PLCC 28 E1 E MILLIMETERS INCHES DIM A A1 B MIN NOM MAX 4.20 2.29 0.33 4.45 2.79 0.41 MIN NOM MAX 4.57 0.165 0.175 0.180 3.04 0.090 0.110 0.120 0.53 0.013 0.016 0.021 D/E 12.32 12.45 12.57 0.485 0.490 0.495 D1 D1/E1 11.43 11.51 11.58 0.450 0.453 0.456 D2/E2 9.91 10.41 10.92 0.390 0.410 0.430 e 1.19 1.27 1.35 0.047 0.050 0.053 D B e A1 D2/E2 A 28 DS40F3 -XO &21),'(17,$/ APPLICATIONS +5V + 68 F RGND 28 Control & Monitor 1 12 11 RV+ 5 7 6 Frame Format Encoder/ Decoder 8 3 4 2 9 XTL 10 CLKE ACLKI LOS CS61535A 0.1 F 21 RV+ 15 TV+ + 1.0 F TGND +5V 100 k SCLK CS INT 27 26 23 24 25 P Serial Port DPM SDI SDO MODE RPOS RNEG RCLK TPOS CS61535A IN HOST MODE RTIP 19 R1 20 17 18 16 13 0.47 F R2 CT 2:1 RECEIVE LINE RRING MTIP TNEG TCLK XTALIN XTALOUT RGND 22 MRING TRING TGND 14 TTIP TRANSMIT LINE DEVICE CS61535A FREQUENCY MHz 1.544 2.048 2.048 CABLE 100 120 75 R1&2 200 240 150 Transmit Transformer 1:1.15 1:1.26 1:1 Figure A1. Host Mode Configuration Line Interface )LJXUHV $ $ V KRZ W KH W \SLFDO FRQ ILJXUDWLRQV IRU L QWHUIDFLQJ W KH , & WR D OLQH WKURXJK WUD QVPLW DQG UHFHLYH WUDQVIRUPHUV 7KH U HFHLYHU WU DQVIRUPHU L V FHQ WHU W DSSHG D QG FHQWHU JURXQGHG ZLWK UHVLVWRUV EHWZHHQ WKH FHQWHU WDS DQG HDFK OHJ RQ WKH ,& VLGH 7KHVH UHVLVWRUV SURYLGH WKH WHUPLQDWLRQ IRU WKH OLQH )LJXUHV $$ VKRZ D ) FDSDFLWRU LQ VHULHV ZLWK WKH WU DQVPLW WU DQVIRUPHU SU LPDU\ 7K LV FD SDFLWRU L V QHHGHG WR SUH YHQW DQ \ EX LOGXS L Q WK H DS40F3 FRUH RI WK H WUDQVIRUPHU GXH WR DQ\ '& LPEDODQFH WKDW P D\ EH SU HVHQW DW WKH GL IIHUHQWLDO R XWSXWV 77,3 D QG 7 5,1* ,I '& VD WXUDWHV WKH WUD QV IRUPHU D ' & RI IVHW Z LOO U HVXOW GX ULQJ W KH WUDQVPLVVLRQ RI D V SDFH ]HUR D V W KH W UDQVIRUPHU WULHV W R GX PS WK H FK DUJH D QG U HWXUQ WR H TXLOLE ULXP 7 KH EOR FNLQJ F DSDFLWRU ZL OO N HHS ' & FXUUHQW IURP IORZLQJ LQ WKH WUDQVIRUPHU Selecting an Oscillator Crystal 6SHFLILF FU \VWDO S DUDPHWHUV DU H U HTXLUHG I RU SURSHU RSH UDWLRQ RI WK H &6 $ Refer to 29 -XO &21),'(17,$/ +5V + 68 F RGND 28 1 Control & Monitor 26 27 12 11 5 7 6 Frame Format Encoder/ Decoder 8 3 4 2 9 XTL CS61535A 0.1 F 21 RV+ 15 TV+ + 1.0 F TGND TAOS ACLKI RLOOP LEN0 23 24 25 LLOOP LOS DPM MODE RPOS RNEG RCLK TPOS TNEG TCLK LEN1 LEN2 Line Length Setting CS61535A IN HARDWARE MODE RTIP 19 R1 20 R2 CT 2:1 RECEIVE LINE RRING MTIP MRING TRING 17 18 16 13 0.47 F TRANSMIT LINE XTALIN XTALOUT RGND 22 TGND 14 TTIP 10 Figure A2. Hardware Mode Configuration +5V + 68 F RGND 17 18 6 28 Control & Monitor 1 26 27 12 11 5 4 7 Frame Format Encoder/ Decoder 8 3 2 9 XTL 0.1 F 21 RV+ 15 TV+ + 1.0 F TGND RCODE PCS BPV LEN0 23 24 25 TAOS ACLKI RLOOP LLOOP LEN1 LEN2 Line Length Setting LOS AIS MODE TCODE RDATA CS61535A IN EXTENDED HARDWARE MODE RTIP 19 R1 20 R2 CT 2:1 RECEIVE LINE RRING RCLK TDATA TCLK XTALIN XTALOUT RGND 22 TGND 14 TRING 16 13 0.47 F TRANSMIT LINE TTIP 10 Figure A3. Extended Hardware Mode Configuration 30 DS40F3 -XO &21),'(17,$/ CS61535A Appendix A for crystal specifications Interfacing The CS61535A With the CS62180B T1 Transceiver 7R LQWHUIDFH ZLWK WKH &6% FRQQHFW WKH GH YLFHV D V V KRZQ L Q ) LJXUH $ ,Q WKL V FDV H WKH &6$ DQG &6% DUH LQ +RVW 0RGH FRQ WUROOHG E\ D PLFURSURFHVVRU VHULDO LQWHUIDFH ,I WKH &6$ LV XV HG LQ +DUGZD UH 0RGH WK HQ WK H &6$ 5&/. RXWSXW PXVW EH LQYHUWHG EHIRUH EHLQJ LQSXW WR WKH &6% ,I WKH &6$ LV XVHG LQ ([WHQGHG +DUGZDUH 0RGH WKH &6$ 5&/. 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DQG QV RI KRO G WLPH RQ WKHVH LQSXWV DI 31 TO HOST CONTROLLER V+ 1.544 MHz CLOCK SIGNAL 100k ACLKI TCLK TPOS V+ 100k CLKE SCLK CS SDO SDI INT RGND 0V +5V 0.1uF V+ 22k 68uF + SCLK SDO SDI CS TCLK TPOS TNEG RNEG RPOS RCLK CS62180B TNEG MODE RNEG RPOS RCLK RV+ CS61535A Figure A4. Interfacing the CS61535A with the CS62180B (Host Mode) CS61534 Compatibility 7KH &6 $ LV S LQ F RPSDWLEOH Z LWK W KH &6 7KH &6$ KDV JUHDWHU MLWWHU WROHU DQFH IRU ERWK WUDQV PLWWHU DQG UHFHLYHU DQG LW SURYLGHV P RUH M LWWHU D WWHQXDWLRQ V WDUWLQJ D W M LWWHU IUHTXHQFLHV RI +] 7K H JUH DWHU MLW WHU W ROHUDQFH DQG DWWHQXDWLRQ L Q WK H WU DQVPLW S DWK P DNHV WKH &6$ PRUH VXLWDEOH IRU &&,77 GHPXOWLSOH[ DS40F3 -XO &21),'(17,$/ WHU WKH IDO OLQJ HGJ H RI 7 &/. 7 KH &6 UH TXLUHV QV RI KR OG WL PH RQ 7 326 DQ G 7 1(* DIWHU W KH ID OOLQJ H GJH RI 7 &/ D QG QV RI V HWXS WLPH / 26 RF FXUV DIWH U FRQ VHFXWLYH ]HURV RQ WK H &6 )RU W KH & 6$ / 26 RF FXUV DIW HU ]HURV 6L QFH WKH &6 $ UHFH LYHUV D UH FR QWLQX RXVO\ FDO LEUDWHG WK HUH LV QR QH HG WR LVVXH D UHVHW WR LQL WLDOL]H WK H U HFHLYHU W LPLQJ D V Z LWK W KH &6 Using the CS61535A for SONET 7KH &6$ FDQ EH DSSOLHG WR 621( 7 97 DQG 97 LQ WHUIDFH F LUFXLWV DV V KRZQ LQ )L J XUH $ 7KH 621(7 GDWD UDWH LV 0+] DQG KDV E LWV S HU IUD PH XV SH U IUD PH $Q LQGLYLGXDO 7 IUDPH ELWV SHU IUDPH RU 3&0 CS61535A IUDPH ELWV SHU IUDPH KDV LWV GDWD PDSSHG LQWR WKH E LW 6 21(7 IU DPH 7 KH P DSSLQJ GRHV QR W U HVXOW LQ D XQ LIRUP V SDFLQJ EHW ZHHQ VXFHVVLYH 7 RU ( ELWV 5DWKHU IRU ORFNHG 97 DSSOLFDWLRQV JDSV DV ODUJH DV 7 ELW SHULRGV RU ( EL W SH ULRGV FD Q H[L VW EHWZHHQ V XFFHVVLYH ELWV : LWK IO RDWLQJ 97 V WKH JDS V F DQ E H HYHQ ODUJHU 7KH FL UFXLW L Q ) LJXUH $ HOL PLQDWHV WKH GHP XOWL SOH[LQJ MLWWHU LQ D WZ RVWHS DSS URDFK 7KH I LUVW VWHS XV HV D ) ,)2 ZK LFK LV ILOOHG DW D 0+] UDWH ZKHQ 7 RU ( ELWV DUH SUHVHQW DQG ZKLFK LV HPSWLHG DW D VXEPXOWLSOH RI WKH UDWH 7KH ),)2 LV H PSWLHG R QO\ ZKHQ LW F RQWDLQV G DWD :KHQ WK H ),)2 LV HPSW \ WK H RXW SXW FORFN LV QRW SXOVHG 7KH V XEPXOWLSOH UD WH FKRVHQ VKRXOG E H V OLJKWO\ IDVWHU WKDQ WKH WDUJHW UDWH RU 0+] EXW DV FORVH WR WKH WDU JHW U DWH DV SRV VLEOH ) RU 51.84 MHz Div By TCLK1 Empty 6480 to 193 bit (or 256 bit) Mapping Circuit FIFO Write Clock TSER TCLK2 TPOS TNEG Jitter Attenuator Driver TSER CS62180B FIFO RSER RPOS RNEG RCLK2 RCLK2 CS61535A Receiver RSER RCLK1 Figure A5. SONET Application 32 DS40F3 -XO &21),'(17,$/ ORFNHG 97 RS HUDWLRQ 7DEOH $ V KRZV SR WHQWLDO VXEPXOWLSOH G DWD UDWH V DQ G WK H LP SDFW RQ WK RVH UDWHV RQ WKH PD[LPXP JDS LQ WKH RXWSXW FORFN RI WKH ), )2 DQG GHSWK RI ) ,)2 UHTXLUHG ) ,)2 GHSWK ZLOO KD YH WR EH LQF UHDVHG IRU IORD WLQJ 97 RSHUDWLRQ ZLWK ELW V RI ),)2 GHSWK EHLQJ DGGHG IRU HDFK SRLQWHU DOLJQPHQW FKDQJH WKDW FDQ RFFXU 7KH R EMHFWLYH WKDW V KRXOG EH P HW LQ SLFNLQJ D ),)2 G HSWK D QG F ORFN GL YLGHU LV NH HS W KH PD[L PXP JDS RQ WKH RXWSXW RI WKH ),)2 DW ELW V RU OHVV 7ZHOYH ELWV LV WKH PD[LPXP MLWWHU ZKLFK FDQ EH LQSXW WR WKH &6$V MLWWHU DWWHQXDWRU ZLWK RXW FDXV LQJ WKH RYHU IORZXQGHIORZ SURWHFWLRQ FLUFXLW WR RS HUDWH 7KH &6$ WKH Q UHPRYHV WKH UHPDLQLQJ MLWWHU IURP WKH VLJQDO 7KH U HFHLYH SDWK DOV R U HTXLUHV D ELW P DSSLQJ IURP RU ELWV WR ELWV 7KLV PDSSLQJ UHTXLUHV DQ LQSXW EXI IHU ZLW K WKH VDPH GH SWK DV XVH RQ WKH WUDQVPLW SDWK 7KLV EXIIHU DOVR DEVRUEV WKH R XWSXW M LWWHU JH QHUDWHG E\ W KH & 6$V GLJLWDO FORFN UHFRYHU\ Target Rate (MHz) 1.544 1.544 2.048 Clock Divider 32 33 25 Resultant Rate (MHz) 1.620 1.571 2.074 CS61535A Transformers 5HFRPPHQGHG WUDQ VPLWWHU DQG U HFHLYHU WUDQV IRUPHU VS HFLILFDWLRQV I RU WK H &6 $ DU H VKRZQ LQ 7DEOH $ 7KH WUDQVIRUPHUV LQ 7DEOH $ KDYH E HHQ W HVWHG D QG UHFRPPHQGHG I RU XVH ZL WK WKH &6$ 5HIHU WR WKH 7 HOHFRP 7 UDQV IRUPHU 6HOHFWLRQ *XLG H IRU GHW DLOHG V FKHPDWLFV ZKLFK VKRZ KRZ WR FRQ QHFW WKH OLQ H LQWHUIDFH ,& ZLWK D SDUWLFXODU WUDQVIRUPHU ,Q DSSOLFDWLRQV ZLWK WKH &6$ ZKHUH LW LV DG YDQWDJHRXV WR XVH D VLQJOH WUDQVPLWWHU WUDQVIRUPHU IRU ERWK DQG ( DSSOLFDWLRQV D WUDQVIRUHU PD\ EH XV HG $OWK RXJK WUDQ VPLWWHU UH WXUQ ORVV ZLOO EH UHGXFHG IRU DSSOLFDWLRQV WKH SXOVH DP SOLWXGH Z LOO EH FRUUHFW DFU RVV D ORDG Maximum Gap bits (s) 6.2 10 3.9 6 3.4 7 FIFO Depth Required 21 26 34 Table A1. Locked VT FIFO Analysis Parameter Turns Ratio CS61535A Receiver 1:2 CT 5% CS61535A Transmitter 1:1 1.5 % for 75 E1 1:1.15 5 % for 100 T1 1:1.26 1.5 % for 120 E1 1.5 mH min. @ 772 kHz 0.3 H max. @ 772 kHz 0.4 H max. @ 772 kHz 18 pF max. 16 V-s min. for T1 12 V-s min. for E1 Primary Inductance Primary Leakage Inductance Secondary Leakage Inductance Interwinding Capacitance ET-constant 600 H min. @ 772 kHz 1.3 H max. @ 772 kHz 0.4 H max. @ 772 kHz 23 pF max. 16 V-s min. for T1 12 V-s min. for E1 Table A2. Transformer Specifications DS40F3 33 -XO &21),'(17,$/ CS61535A Application RX: T1 & E1 TX: T1 TX: E1 (75 & 120 ) RX &TX: T1 RX &TX: E1 (75 & 120 ) RX &TX: T1 RX &TX: E1 (75 & 120 ) RX : T1 & E1 TX: E1 (75 & 120 ) Turns Ratio(s) 1:2CT Manufacturer Pulse Engineering Schott Bel Fuse Pulse Engineering Schott Bel Fuse Pulse Engineering Schott Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Pulse Engineering Part Number PE-65351 67129300 0553-0013-HC PE-65388 67129310 0553-0013-RC PE-65389 67129320 0553-0013-SC PE-65565 0553-0013-7J PE-65566 0553-0013-8J PE-65765 S553-0013-06 PE-65766 S553-0013-07 PE-65835 PE-65839 Package Type 1.5 kV through-hole, single 1:1.15 1.5 kV through-hole, single 1:1.26 1:1 1:2CT 1:1.15 1:2CT 1:1.26 1:1 1:2CT 1:1.15 1:2CT 1:1.26 1:1 1:2CT 1:1.26 1:1 1.5 kV through-hole, single 1.5 kV through-hole, dual 1.5 kV through-hole, dual 1.5 kVsurface-mount, dual 1.5 kV surface-mount, dual 3 kV through-hole, single EN60950, EN41003 approved 3 kV through-hole, single EN60950, EN41003 approved Table A3. Recommended Transformers For The CS61535A 34 DS40F3 CS61535A APPENDIX A. RECOMMENDED CRYSTAL SPECIFICATIONS Cirrus Logic telecommunication devices that offer jitter attenuation require crystals with specifications for frequency pullability. The crystal oscillation frequency is dictated by capacitive loading, which is controlled by the chip. Therefore, the crystals must meet the following specifications. 6.176 MHz Crystal Performance Specifications Parameter Total Frequency Range Operating Frequency Cload = 11.6 pF Cload = 19.0 pF Cload = 37.0 pF (Note 1) (Note 2) (Note 3) (Note 2) Min 6.176803 6.175846 Typ 370 6.176000 Max 390 6.176154 6.175197 Units ppm MHz MHz MHz 8.192 MHz Crystal Performance Specifications Parameter Total Frequency Range Operating Frequency Cload = 11.6 pF Cload = 19.0 pF Cload = 37.0 pF (Note 1) (Note 2) (Note 3) (Note 2) Min 8.192410 8.191795 Typ 210 8.192000 Max 245 8.192205 8.191590 Units ppm MHz MHz MHz Notes: 1. With Cload varying from 11.6 to 37.0 pF at a given temperature. 2. Measured at -40 to 85C. 3. Measured with Saunders 150D meter at 25 C. DS40F3 35 CS61535A REVISION HISTORY Revision F3 Date Jul '09 Changes Removed development system info. (No longer supported). Removed PDIP option. Changed PLCC package option to lead-free. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 36 DS40F3 |
Price & Availability of CS61535A09
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